EnSilica launches the eSi-RISC configurable processor cores EnSilica boosts its front-end IC design services with the launch of new eSi-RISC configurable processor cores, offering a scalable architecture for low-cost feature-rich embedded applications.
Design and reuse an impossible dream, panelists question A panel session at the IP-ESC 2009 Conference this week in Grenoble, France, examined IP design and reuse from a business and technology perspective and urged IP and SoC providers to reach compromises.
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