BATH, England — PicoChip Designs Ltd., a fabless chip company focused on wireless basestation applications, is getting ready to tape-out its fourth generation of multicore DSP chips while also planning an architectural refresh to allow it to take chips to higher performance.
The PicoChip multicore array is at the heart of PicoChip's product offering. It is on to this array and connective fabric that the company mounts software to implement voice and data communications for numerous standards, including WiMax, HSPA, LTE, CMDA2000 and TD-SCDMA.
Peter Claydon, chief operating officer and cofounder, speaking at the 'Born Global' one-day meeting organized here by the Silicon SouthWest promotional group, said the PicoArray has remained more or less at the same level of complexity since launch at between about 250 and 300 cores.
Claydon said the architecture can scale with silicon miniaturization but that so far PicoChip has chosen to take the die-shrink advantage with a move from 130-nm to 90-nm. The next chip, designed for manufacture by Taiwan Semiconductor Manufacturing Co. Ltd. using a 65-nm process, is due to tape-out in August, Claydon said. Claydon told EE Times that the PicoArray has always been run at the relatively modest clock frequency of 160-MHz.
Claydon said: "Within the next couple of years we will be doing an architectural refresh."
In fact, the number of cores included in the PicoArry has reduced over time.
