London -- ARM Holdings plc took its Cortex family multicore last week with the unveiling of the Cortex-A9. The move, announced at the ARM Developers' Conference in Santa Clara, Calif., follows up on a July announcement of multiprocessing extensions to the ARMv7 architecture. CEO Warren East had been dropping hints since early 2006 that a multiprocessor core would join the Cortex family.
The single-core Cortex-A9 is roughly equivalent in performance to the established Cortex-A8 processor. But the A9 is also available with two, three or four cores clustered to provide more than 8,000 Dhrystone Mips of symmetric-multiprocessing (SMP) performance. The core is synthesizable and is expected to be capable of clocking in excess of 1 GHz in a leading-edge process, although the greatest power efficiencies will come as clocks are slowed or cores are switched off.
Further, the architecture is scalable beyond four cores. "Licensees can put down more than one cluster on a chip if they want," said John Goodacre, multiprocessing program manager at ARM. The intellectual-property provider is aiming the architecture at such applications as HDTV set-top boxes, home server engines and mobile Internet handsets.
Several companies have already licensed the Cortex-A9, including NEC Electronics, Nvidia, Samsung, STMicroelectronics and Texas Instruments. But there's no silicon yet, and deliverables to ARM partners will not be finalized until the first quarter, according to Goodacre.
The A9 core itself is a refinement of the Cortex-A8. "There are a couple of extra instructions in support of multiprocessing, but it is backward compatible," said Goodacre. Like the A8, the A9 it is superscalar, with a multi-issue eight-stage pipeline. Early branch resolution is evaluated asynchronously to instruction fetch, with continuous fetch and decode of two instructions allowed per clock cycle.
But the A9 pipeline goes further by supporting out-of-order instruction dispatch and completion.
The new architecture adds to ARM's established multiprocessor capability with an accelerator coherence port supporting hardware accelerators and DMA units; support for TrustZone technology, with interrupt virtualization; and a generalized interrupt controller.
As a full-fledged ARMv7 device, the A9 MPcore supports Thumb2 instructions, TrustZone, a floating-point unit and Neon, ARM's single instruction multiple-data extension for streaming-media processing. The instruction and data L1 caches associated with each core incorporate cache-coherency support, synchronized via a snoop control unit. A local coherence bus links to the SCU.
In a break with tradition, the A9 is being offered as a synthesizable core from the start. "It's [also] configurable, in terms of FPU or Neon additions to the processor, cache size, interrupt scheme and interface," said Goodacre.
Even though ARM has not finalized the design, the company is licensing it. "We have delivered beta [design files] to licensees. Q1 next year is [the targeted] signoff from ARM," said Goodacre.
That would suggest the licensees could need another year to 18 months to get their silicon made. "I would expect the first devices [using the Cortex-A9] on the shelves at the end of 2009 and volume in 2010," said Goodacre.
It is also expected that the design, currently being benchmarked against 65-nanometer design files, will debut in 45-nm silicon.
As for OS support, Goodacre cited successful reference implementations running on the ARM11 MPcore, including Nucleus, from Mentor Graphics Corp.; the generic Linux kernel; QNX; Mobilinux, from MontaVista Software Inc.; and an implementation from Japan's eSol Co. Ltd. that blends asymmetric and symmetric multiprocessing. "Symbian isn't officially supporting multiprocessing on ARM11, but they have it running in the lab," said Goodacre.
