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[Part 2 covers quantization, noise shaping, and effective number of bits (ENOB) for sigma-delta ADCs. Part 4 explains how flash converter and subranging (i.e., pipelined) ADCs work.]
All sigma-delta ADCs have a settling time associated with the internal digital filter, and there is no way to remove it. In multiplexed applications, the input to the ADC is a step function if there are different input voltages on adjacent channels. In fact, the multiplexer output can represent a full-scale step voltage to the sigma-delta ADC when channels are switched. Adequate filter settling time must be allowed, therefore, in such applications. This does not mean that sigma-delta ADCs shouldn't be used in multiplexed applications, just that the settling time of the digital filter must be considered.
For example, the group delay through the AD1877 FIR filter is 36/fs, and represents the time it takes for a step function input to propagate through one-half the number of taps in the digital filter. The total time required for settling is therefore 72fs, or approximately 1.5 ms when sampling at 48 kSPS with a 64× oversampling rate.
Figure 3-18: AD1877 16-Bit, 48 kSPS Stereo Sigma-Delta ADC FIR Filter Characteristics.
In other applications, such as low frequency, high resolution 24-bit measurement sigma-delta ADCs (such as the AD77xx series), other types of digital filters may be used. For instance, the SINC3 response is popular because it has zeros at multiples of the throughput rate. For instance, a 10 Hz throughput rate produces zeros at 50 Hz and 60 Hz, which aid in ac power line rejection.
So far we have considered only sigma-delta converters that contain a single-bit ADC (comparator) and a single-bit DAC (switch). The block diagram of Figure 3-19 shows a multibit sigma-delta ADC that uses an n-bit flash ADC and an n-bit DAC. Obviously, this architecture will give a higher dynamic range for a given over-sampling ratio and order of loop filter. Stabilization is easier, since second-order and higher loops can be used. Idling patterns tend to be more random, thereby minimizing tonal effects.
The real disadvantage of this technique is that the linearity depends on the DAC linearity, and thin film laser trimming is generally required to approach 16-bit performance levels. This makes the multibit architecture extremely difficult to implement on sigma-delta ADCs. It is, however, currently used in sigma-delta audio DACs (AD1852, AD1853, AD1854) where special "bit scrambling" techniques are used to ensure linearity and eliminate idle tones.
Figure 3-19: Multibit Sigma-Delta ADC.
The Σ-Δ ADCs that we have described so far contain integrators, which are low-pass filters, whose pass band extends from dc. Thus, their quantization noise is pushed up in frequency. At present, most commercially available Σ-Δ ADCs are of this type (although some that are intended for use in audio or telecommunications applications contain band-pass rather than low-pass digital filters to eliminate any system dc offsets). But there is no particular reason why the filters of the Σ-Δ modulator should be LPFs, except that traditionally, ADCs have been thought of as being baseband devices, and that integrators are somewhat easier to construct than band-pass filters. If we replace the integrators in a Σ-Δ ADC with band-pass filters (BPFs) as shown in Figure 3-20, the quantization noise is moved up and down in frequency to leave a virtually noise-free region in the pass band (see Reference 1). If the digital filter is then programmed to have its pass band in this region, we have a Σ-Δ ADC with a band-pass, rather than a low-pass characteristic. Such devices would appear to be useful in direct IF-to-digital conversion, digital radios, ultrasound, and other undersampling applications. However, the modulator and the digital BPF must be designed for the specific set of frequencies required by the system application, thereby somewhat limiting the flexibility of this approach.
In an undersampling application of a band pass Σ-Δ ADC, the minimum sampling frequency must be at least twice the signal bandwidth, BW. The signal is centered around a carrier frequency, fc. A typical digital radio application using a 455 kHz center frequency and a signal bandwidth of 10 kHz is described in Reference 1. An oversampling frequency Kfs = 2 MSPS and an output rate fs = 20 kSPS yielded a dynamic range of 70 dB within the signal bandwidth.
Figure 3-20: Replacing Integrators with Resonators Gives a Band-Pass Sigma-Delta ADC.
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