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Part one introduces the hardware used for debugging, the debugging challenges facing DSP programmers, and debugging methodologies.
Part three explains how emulators control programs on the DSP through functions such as breakpoints and single-stepping.
Introduction to JTAG
One of the disadvantages of shrinking technology is that testing small devices effectively gets exponentially more complex. When circuit boards were large, boards were tested using techniques such as a bed-of-nails. This was a technique that used small spring-loaded test probes to make connections with solder pads on the bottom of the board. Such test fixtures were custom made, expensive, and inefficient; and still much of the testing could not be performed until the design was complete.
The problems with bed-of-nails testing were exacerbated as board dimensions got smaller and surface mount packaging technology improved. Further, if devices were mounted on both sides of a circuit board, there were no attachment points left for the test equipment.
Boundary scan
A group of European electronics companies joined forces in 1985 to find a solution to these problems. The consortium called themselves the Joint Test Action Group (JTAG). The result of their work was a specification for performing boundary scan hardware testing at the integrated circuit level. In 1990, that specification resulted in a standard (IEEE 1149.1) that specifies the details of access to any chip with a so-called JTAG port.
Boundary scan technology allows extensive debugging and diagnostics to be performed on an embedded system through a small number of dedicated test pins. Signals are scanned into and out of the I/O cells of a device(s) serially to control its inputs and test the outputs under various conditions. Today, boundary scan technology is probably the most popular and widely used design-for-test technique in the industry.
Test pins
Devices communicate to the world via a set of I/O pins. By themselves, these pins provide very limited visibility into what is going on inside the device. However, devices that support boundary scan contain a shift register cell for each signal pin of the device. These registers are connected in a dedicated path around the boundary (hence the name) of the device, as shown in Figure 5. This creates a virtual access capability that circumvents the normal inputs and provides direct control of the device and detailed visibility at its outputs.
Figure 5 A standard integrated circuit with a JTAG boundary scan
During testing, I/O signals for the device enter and leave the chip through the boundary scan cells. The boundary scan cells can be configured to support external testing for testing the interconnection between chips or internal testing for testing the internal logic within the chip.
In order to provide the boundary scan capability, IC vendors have to add additional logic to each of their devices, including scan registers for each of the signal pins, a dedicated scan path connecting these registers, four (and an optional fifth) additional pins (more below), plus additional control circuitry.
The overhead for this additional logic is minimal and generally well worth the price in order to provide efficient test capability at the board level. The boundary scan control signals, collectively referred to as the test access port (TAP), define a serial protocol for scan based devices:
- TCK/clock – To synchronize the internal state machine operations.
- TMS/mode select – Sampled at the rising edge of TCK to determine the next state.
- TDI/data in – When the internal state machine is in the correct state, this signal is sampled at the rising edge of TCK and shifted into the device's test or programming logic.
- TDO/data out – When the internal state machine is in the correct state, this signal represents the data shifted out of the device's test or programming logic and is valid on the falling edge of TCK.
- TRST/reset (optional) – When driven low, the internal state machine advances to the reset state asynchronously.
The TCK, TMS, and TRST input pins drive a 16-state TAP controller state machine. The TAP controller manages the exchange of data and instructions. The controller advances to the next state based on the value of the TMS signal at each rising edge of TCK. With proper wiring, multiple ICs or boards can be tested simultaneously. An external file known as the boundary-scan description language (BSDL) file defines the capabilities of any single device's boundary-scan logic.
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