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FPGA synthesis can be a leverage point in your design flow



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Courtesy of Programmable Logic DesignLine

Introduction 

FPGA design starts are on the rise due to the lower startup costs and re-programmability that FPGA devices can provide. However, large, complex FPGA devices pose significant challenges to an FPGA project team. Only by following sound design flow practices can FPGA designers manage their projects effectively.

Modern design flows have FPGA synthesis positioned at the critically important junction between design creation and physical implementation. Because of this strategic placement in the design process, FPGA synthesis can provide significant leverage in achieving project cost, time and quality goals. In this article, we will discuss how FPGA synthesis tools can help designers achieve their goals efficiently and effectively.

Choosing a design flow that leverages modern tools and techniques

Most development projects are driven by a familiar mantra: "faster, sooner, better." For FPGA designers, this translates into reducing time to market and project costs while meeting aggressive performance goals. Moreover, many projects require FPGA designers to follow strict certifiable process standards and at the same time manage project costs and delays.

But FPGA designers don't need to reinvent the wheel when developing a process. By borrowing proven practices from the ASIC design playbook they can achieve their project objectives without incurring huge NRE costs. In the discipline of ASIC design there is a strong emphasis on using the right methodology and tools. By adhering to this principle, engineering teams can achieve improved performance in every aspect of an FPGA project including technical results, schedule, productivity and cost. Recognizing this, FPGA designers are already turning to advanced methodologies, techniques and tools.

These modern FPGA design flows encourage efficient design practices including:

  • Maintaining vendor independence
  • Raising the level of design abstraction
  • Using debug capabilities that span the flow
  • Using advanced verification techniques
  • Figure 1 depicts a typical FPGA design flow. FPGA synthesis is the crucial step in which abstract high-level design ties in with the detailed physical design processes. Without investing excessive time and effort, designers can leverage the benefits of FPGA synthesis tools to achieve high-quality of results.

    Figure 1. Synthesis is central to the modern hardware design flow (click on image to enlarge).



    Page 2: Fostering vendor-independent design  

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    Related Links:
  • Ensuring Safe Design for Mil-Aero & Safety-Critical Applications
  • High-level C-to-Silicon synthesis for Altera and Xilinx FPGAs
  • IPextreme teams with Mentor Graphics on 8051 cores
  • FPGA-based rapid prototyping of ASIC, ASSP, and SoC designs
  • How to improve FPGA-based ASIC prototyping with SystemVerilog


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