Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1. (The middle of the family range is filled out by the AV 404V, AV 406V, and AV 407V). The AV 40xV family subsystems are intended for compression-centric applications such as camera phones, portable media players, DVB-H and DVD players.
The new subsystems are ARC's first to target high-quality video encode, which ARC believes has become a requirement of many multimedia applications. All AV 40xV subsystems include a CPU core and a two-dimensional DMA engine. They also include varying assortments of SIMD media coprocessors as well as hardware accelerators for motion estimation, entropy encoding, and entropy decoding. ARC also offers software for many video, imaging, and audio codecs.
ARC's initial business focus was on configurable RISC CPUs, and the new video subsystems hew to that heritage in two ways. First, each subsystem includes an ARC700 family CPU. Second, each subsystem is configurable by the licensee in a few respects. For example, licensees can select among several ARC700 CPU family members, and can add custom instructions to the CPU and tweak the cache size.
According to ARC, the AV 417V can encode H.264 Baseline Profile (D1 resolution, 30 fps, 10 Mbps) at 200 MHz, and is also capable of MPEG-4 Simple Profile/Advanced Simple Profile encode, H.264 Baseline Profile decode, and MPEG-4 Advanced Simple Profile decode. ARC estimates the die size of the AV 417V to be 4.95 sq. mm (post-layout), including 32 KB instruction and data caches, in a 90 nm "G" process using Virage libraries.
For more analysis of ARC's AV 40xV video subsystems, see InsideDSP.
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