On May 15, Xilinx Inc. unveiled its new Virtex-5 line of field programmable gate arrays (FPGAs). The product line will consist of four distinct families, each targeting a specific class of applications. While all four families share the same basic architecture, each will have a different mixture of hard-wired blocks and I/O features geared for its targeted applications. The three currently sampling devices are from the LX family and target high-speed logic applications. The remaining three families are slated to become available in sample quantities during the second half of 2006 and the first half of 2007, and will target embedded processing, digital signal processing, and serial-connectivity-intensive applications. Significant changes from the Virtex-4 family include migration from a 90 nm process to a 65 nm triple-oxide process, improvements to the logic cell interconnect architecture, and enhancements to hard-wired blocks.
1. DSP48E hardwired DSP block.
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A feature of particular interest to FPGA users targeting DSP applications is the DSP48E hard-wired data path block, an enhanced version of the DSP48 block used in the Virtex-4 line. (See Figure 1.) Applications that Xilinx believes will benefit from the DSP48E include medical imaging, baseband processing for emerging communications standards such as 3G and 4G cellular, and defense applications such as beamforming and radar.
For BDTI's analysis of the Virtex-5, see Inside DSP.
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