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Part 1 looks at the design of the SIMD architecture.
Customizing the LE2: The ITUVECTOR Plug-in Datapath
A unique aspect of the LE2 is its ability to adapt to various workloads through the use of C-designed plug-in vector datapaths. This section elaborates on the design of a custom vector ISA for accelerating the G723.1 and G729.A speech coding standards and the design of a custom datapath to implement that ISA.
The G.7231.1 [13] and the G.729A [14], standard speech coding algorithms, as recommended by the ITU-T, belong to the category of linear-prediction analysis-by-synthesis (LPAS) speech coders. The G.729A algorithm is used to code speech signals at 8 kbit/s using a reduced complexity version of the conjugate-structure, algebraic-code-excited linear-prediction (CS-ACELP) G.729 recommendation. The coder operates on speech frames of 10ms where the speech signal is analyzed to extract the code-excited linear-prediction (CELP) model parameters, which are then encoded and transmitted. The decoder receives the parameters, which are then used to reconstruct the speech signal.
The G.723.1 standard was developed to form part of the H.324 standard for multimedia compression and transmission. This recommendation specifies a dual-rate codec which operates at either 5.3 Kbit/s or 6.3 Kbit/s. Both these rates use different techniques to determine the parameters to encode and transmit. The higher bit-rate uses the maximum likelihood quantization (MPC-MLQ) method while the lower bit-rate, like the G.729A, uses the ACELP method. Such coding schemes have been widely adopted as they produce high quality speech at low bit-rates, despite a burden of higher computational complexity.
These ITU codes have been studied extensively [15] [16] and vector implementations have been derived. These vector forms are based on the BASICOP C-level functions, as specified by the ITU-T. This optimization process has taken place after profiling the codes with the ITU-T supplied workloads and manually identifying the amount of data level parallelism (DLP). The profiling results for G729.A and G723.1 are shown in tables 2 and 3 respectively:
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Table 2. G729.A function-level profiling (Simplescalar)
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Table 3. G723.1 function-level profilinig (Simplescalar)
Figs. 5 through 14 show the relative instruction count, with the base case being the un-modified ITU-T reference codes, after the introduction of that vector ISA.
It should be noted that the benefits realized in Figures 5 through 14 relate to the full deployment of that ISA. The ITUVECTOR plug-in, discussed later, demonstrates the implementation of the L_MAC functionality only, for reasons of brevity.
ESL Design of the ITUVECTOR Unit with the CebaTech C2R Compiler
Further to the high level (macro-architecture level) design style enabled with C2R, there are instances where more fine-grained control over clocking and resource allocation is needed in order to build arbitrary pipelined datapaths. Such blocks can be used both stand-alone, in RTL-based designs, as well as accessed from within a higher level macro-architecture (C2R) system.
Consider the diagram of Fig. 15:
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Figure 15. ITUVECTOR micro-architecture
The figure depicts a 3-stage pipeline that implements the L_MAC operation, as specified by the ITU-T. The schematic includes sufficient detail for an RT level implementation, however the core datapath functionality (L_Mult and L_add) is not quite as straightforward due to the need to be fully ITU-T compliant. Nonetheless, C2R easily synthesizes the design since the reference source is ANSI-C.
The module interface of the ITUVECTOR block above is depicted in Fig. 16:
Figure 16. ITUVECTOR Interface
It is easy to describe such a parametric interface for C2R synthesis. A good way of doing this is via having all input and output signals expressed with record types. In this case, chaniT and chanoT encapsulate the Input and Output interfaces of the ITUVECTOR unit respectively.
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