Comment: Clockless DSP offers superior performance

The converter uses a level-crossing detector that continuously tracks the input (Figure 1). The detector outputs signals indicating the timing and direction of level changes. This data goes through a 16-tap FIR filter that produces an 8-bit word. Figure 2 shows measured results for a voice band system. Note the lack of aliasing—there are no "image" frequencies or beating of input and sampling frequencies. SNR results compare very favorably with conventional architectures, with a noise floor 5.4 dB lower than regular 8-bit systems.

Figure 1. Operation of delta modulator encoding of input, delaying of information, and reconstruction by the first accumulator/multiplier block.

Figure 2. Measured 16-tap FIR LPF response (top) compared to expected response. Output spectrum for a full-scale 2 kHz input (bottom left) and a 35 kHz input -19 dB relative to full-scale (bottom right). Signal quantization: 8b at full scale. Coefficient quantization: 8b.

References
[1] "A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing", Bob Schell, Yannis Tsividis, Columbia University, New York, NY

About the author
Shiv Balakrishnan has more than 25 years of experience in signal processing including 12 years at Tektronix. He has held engineering and technical marketing positions in startups as well as Fortune 500 companies like Philips, Sun and TI. His consulting work spans the range from signal processing system design to market research and competitive analysis. Shiv is named co-inventor on multiple DSP and wireless patents. His undergraduate degree is from the Indian Institute of Technology and graduate studies were at the University of Florida and Purdue University.

COURSE
1. Smart Antennas in Mobile Communications—A Short Tutorial

COURSE
2. Smart Antennas for GSM and DECT

COURSE
3. Introduction Into Modeling with Petri Nets

COURSE
4. FPGA Synthesis of Custom DSP Blocks Using Distributed Arithmetic