ADCs for DSP, part 4

Flash Converters
Flash ADCs (sometimes called parallel ADCs) are the fastest type of ADC and use large numbers of comparators. An N-bit flash ADC consists of 2^N resistors and 2^N–1 comparators arranged as in Figure 3-22. Each comparator has a reference voltage that is 1 LSB higher than that of the one below it in the chain. For a given input voltage, all the comparators below a certain point will have their input voltage larger than their reference voltage and a "1" logic output, and all the comparators above that point will have a reference voltage larger than the input voltage and a "0" logic output. The 2^N–1 comparator outputs therefore behave in a way analogous to a mercury thermometer, and the output code at this point is sometimes called a thermometer code. Since 2^N–1 data outputs are not really practical, they are processed by a decoder to an N-bit binary output.

The input signal is applied to all the comparators at once, so the thermometer output is delayed by only one comparator delay from the input, and the encoder N-bit output by only a few gate delays on top of that, so the process is very fast. However, the architecture uses large numbers of resistors and comparators and is limited to low resolutions and, if it is to be fast, each comparator must run at relatively high power levels. Hence, the problems of flash ADCs include limited resolution, high power dissipation because of the large number of high speed comparators (especially at sampling rates greater than 50 MSPS), and relatively large (and therefore expensive) chip sizes. In addition, the resistance of the reference resistor chain must be kept low to supply adequate bias current to the fast comparators, so the voltage reference has to source quite large currents (>10 mA).

In practice, flash converters are available up to 10 bits, but more commonly they have 8 bits of resolution. Their maximum sampling rate can be as high as 1 GHz, with input full-power bandwidths in excess of 300 MHz.

Figure 3-22: Flash or Parallel ADC.

As mentioned earlier, full-power bandwidths are not necessarily full-resolution bandwidths. Ideally, the comparators in a flash converter are well matched both for dc and ac characteristics. Because the strobe is applied to all the comparators simultaneously, the flash converter is inherently a sampling converter. In practice, there are delay variations between the comparators and other ac mismatches that cause a degradation in ENOB at high input frequencies. This is because the inputs are slewing at a rate comparable to the comparator conversion time.

The input to a flash ADC is applied in parallel to a large number of comparators. Each has a voltage-variable junction capacitance, and this signal-dependent capacitance results in most flash ADCs having reduced ENOB and higher distortion at high input frequencies.

Adding 1 bit to the total resolution of a flash converter requires doubling the number of comparators. This limits the practical resolution of high speed flash converters to 8 bits because of excessive power dissipation.

However, in the AD9410 10-bit, 200 MSPS ADC, a technique called interpolation is used to minimize the number of preamplifiers in the flash converter comparators and also reduce the power (1.8 W). The method is shown in Figure 3-23.

Figure 3-23: "Interpolating" Flash Reduces the Number of Preamplifiers by Factor of Two.

The preamplifiers (labeled "A1," "A2,") are low gain g_m stages whose bandwidth is proportional to the tail currents of the differential pairs. Consider the case for a positive-going ramp input that is initially below the reference to AMP A1, V1. As the input signal approaches V1, the differential output of A1 approaches zero (i.e., A = A), and the decision point is reached. The output of A1 drives the differential input of LATCH 1. As the input signal continues to go positive, A continues to go positive, and B begins to go negative. The interpolated decision point is determined when A = B. As the input continues positive, the third decision point is reached when B = B. This novel architecture reduces the ADC input capacitance and thereby minimizes its change with signal level and the associated distortion. The AD9410 also uses an input sample-and-hold circuit for improved ac linearity.

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