How to optimize power consumption in embedded DSP applications, part 1

For more tips on saving power, see "Optimize performance and power with dynamic power management," "Push performance and power beyond the data sheet," "Processor Power Consumption: Beyond the Data Sheet," and "Designing Low-Power Signal Processing Systems."]

Designers of both wireless and wired systems should be concerned about power efficiency—largely for different reasons. For mobile devices, longer battery life and longer talk or run times are obvious advantages but lowering power requirements can also result in using smaller batteries or choosing a different battery technology. Thermal problems can also be mitigated.

For wired systems, designers can reduce the size of the power supply, cooling requirements, and fan noise. Less often noted is the fact that power efficiency can also make room for additional components that boost performance, particularly when the design team would like to have more than one processor.

Embedded designs that include a DSP processor—or that might if an aggressive system power budget can be met—can conserve power using techniques specific to the DSP, its operating system and its supporting software. Much can be gained in terms of power savings in a DSP or dual processor-design that are beyond the realm of conventional techniques.

This article will include both the conventional techniques and those that are specific to DSPs. To start, however, it is important to define the terms and principles that will be used in the discussion.

Power consumption basics
Total power consumption of a complementary metal-oxide semiconductor (CMOS) circuit is the sum of both active and static power consumption [Ref. 3]:

P_total = P_active + P_static

Active power consumption occurs when a gate is switching from one logic state to another and is the result of switching current (needed to charge internal nodes), and through current (flows when both P and N-channel transistors are both momentarily on). Active power is approximated by:

P_transient ∼ C_pd × F × V_cc² × N_sw

where C_pd is the dynamic capacitance, F is the switching frequency, V_cc is the supply voltage, and N_sw is the number of bits switching.

An additional relationship is that voltage (V_cc) determines the maximum switching frequency (F) for stable operation.

Two important concepts are inherent in these relationships:

• Active power is linearly related to switching frequency and quadratically related to the supply voltage
• Maximum safe switching frequency is determined by the supply voltage. For the purposes of this article, a particular frequency and voltage pair will be referred to as a "setpoint."

While it is well known that reducing the CPU clock will have a proportional savings in active power dissipation, an additional saving can be realized from the quadratic relationship by reducing the voltage—as long as it can be reduced without affecting performance.

For a given task set, however, reducing the CPU clock rate also proportionally extends the execution time of the same task set. Careful analysis of the application is necessary to assure that it meets its real-time requirements.

Static power consumption is caused by transistor leakage. Traditionally, static power consumption of a CMOS circuit has been negligible compared active power. Embedded applications will typically idle the CPU clock during inactivity to eliminate active power and this dramatically reduces total power consumption.

More attention must be paid to static power in future designs, however, because new, higher-performance transistors are bringing significant boosts in leakage currents [Ref. 13].

Page 2: Critical design decisions; power-saving techniques
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