In May, Texas Instruments disclosed its first implementation of the ARM Cortex-A8 processor. Started in 2003 and reportedly involving a team of forty-five engineers in TI's wireless handset chip unit, the implementation represents a massive effort considering the Cortex-A8 is just one element of the complex SoCs designed by TI for cell phones. Typically, ARM cores are implemented using logic synthesis exclusively. For the Cortex-A8, TI instead took the very labor-intensive path of hand crafting many parts of the implementation to squeeze more performance and energy efficiency out of the core. TI's Cortex-A8 implementation will first be used in the company's OMAP3 family of chips. Announced in February, OMAP3 is a family of application processors that mainly target multimedia-rich "smart phones." With OMAP3, TI aims to boost performance on an array of smart phone applications such as video playback, gaming, and email.
1. A floorplan of TI's Cortex-A8 imlementation, showing which portions were implemented using which design methodology. Green and dark blue indicate random logic synthesis (RLS); light blue indicates full custom; white with blue tiling indicates structured data path (SDP) or mix of SDP and RLS.
In TI's implementation of the Cortex-A8, three different design methodologies were used: random logic synthesis, structured data path, and full custom. (See Figure 1.) Random logic synthesis is the most automated methodology and is the approach used exclusively for most processor core implementations on SoCs. With TI's structured data path methodology, logic cell placement is defined by hand at the gate level. For full-custom blocks, circuits were designed at the transistor level with all routing specified by designers. TI also implemented a full-custom clock distribution grid for the Cortex-A8, with repeaters, clock buffers, and power switches allocated to specific bays interspersed throughout the chip.
For BDTI's analysis of TI's Cortex-A8 implementation, see Inside DSP.
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