ASIC manufacturers that cater to low-to-medium volume applications with medium-logic density requirements have developed a class of custom logic device called a structured ASIC. Targeted at mid-range ASIC applications that require better logic density, lower part price, and reduced power consumption than an FPGA can provide but without the high-volume requirements of a standard-cell ASIC, structured ASICs offer advanced CMOS technologies at low to moderate volumes combined with affordable design-cycle costs and low part prices.
Many electronics applications have wrestled with the divergent demands of low-volume production and low costs. For those applications requiring custom IC designs, the problem gets worse. Many military, industrial, medical, and automotive applications simply can't consume the quantity of silicon required by ASIC manufacturers to achieve the compelling cost savings of a high-volume consumer or computing application. However, the pressure to cut costs is not removed simply because the silicon consumption is low.
Most ASICs are driven by a combination of low cost pressure and unique market-specific requirements. Medium logic density, low-power consumption, or small-footprint applications often have no choice but to use advanced standard-cell ASIC technology to minimize power consumption or meet the cost target.
Unfortunately, that advanced ASIC technology has become increasingly impractical and unaffordable for low-volume systems. The total design costs for high-complexity standard-cell ASICs, including tooling costs and engineering labor, now carry enormous development price tags of several millions of dollars or more. The usual alternative, a less-complex field-programmable gate array (FPGA), can carry equally unreasonable price tags in the hundreds to thousands of dollars per part.
However, ASIC manufacturers that cater to mid-range applications have developed a relatively new class of logic device called a structured ASIC. A structured ASIC is a new generation of gate arrays with improvements specifically targeted at reducing the costs of standard-cell ASICs while improving on the logic density and power consumption of an FPGA.
Hybrid structured ASICs take the cost-saving gate array idea one step further, by manufacturing the array in an advanced CMOS process to achieve high densities and low-voltage operation while fabricating the power interconnects in a coarser but less expensive process. Targeted at applications that require better logic density, lower part price, and reduced power consumption than an FPGA can provide but without the high-volume or advanced technology requirements of a standard-cell ASIC, hybrid structured ASICs offer advanced CMOS technologies at low to moderate volumes combined with affordable design-cycle costs and low part prices.
The custom logic conundrum
Leading edge CMOS ASIC processes offer low-voltage operation, clock speeds in the hundreds of megahertz, and high logic density. However, designing in these leading-edge processes is a technically challenging and expensive task. In addition to the difficulty of getting the logic design to operate correctly, the designer must grapple with a variety of problems that are outside the normal bounds of simple logic design.
For example, the standard cell ASIC designer must tackle an environment where the interconnect metal dominates the on-chip delays so that timing "closure" can be enormously difficult to achieve. Each of the thousands of interconnect lines, especially those running in parallel, must be checked for cross-coupling problems and evaluated for signal integrity concerns. The placement and routing of logic cells must take into account the current densities, electric fields, and IR drops along the entire network of interconnect lines to ensure that the operating voltage doesn't drop below specification and that those interconnections don't inadvertently turn into slow-acting fuses.
An advanced ASIC typically takes thirty or more precision layers to create the various circuits and interconnect lines. These layers make up the bulk of the non-recurring engineering (NRE) costs commonly quoted in an ASIC design. These charges – roughly $500,000 to $900,000 depending on the process technology – must be spent again if a design revision occurs for any reason.
Today's wafer foundries make silicon wafers with diameters of 300mm (11.8") and prefer a minimum-order production run that uses 25 of these wafers. By way of example, a modest sized chip design that is 1cm on a side yields about 500 die per wafer, so a minimum order quantity results in 12,500 chips. One minimum order run can sometimes be a lifetime supply of chips for many low-volume applications.
The alternative is to develop the logic design in an FPGA. Because the devices are programmable, FPGAs are very flexible platforms that allow the designer to create and recreate logic designs as necessary, but that flexibility comes at a cost.
Compared to a standard-cell ASIC design, the logic density of an FPGA is smaller by an order of magnitude or more. FPGAs are also very power-hungry and therefore don't work well in a battery-powered system. The densest FPGAs are also the most expensive, sometimes prohibitively so in a cost-sensitive application at $1500 to $2000 per part, reaching the $1M mark with as few as 500 pieces. As such, FPGAs are ideal for prototyping a logic design, but their drawbacks for a production system force designers to look for an alternative solution.
1. Cost vs. Volume of FPGA, Structured ASIC, and Standard Cell ASIC implementations of a 1 million Gate Device.
The Structured ASIC approach
Structured ASICs represent the next-generation of gate arrays with improvements specifically targeted at reducing the mask costs faced by standard-cell ASICs. These improvements come about by reducing the number of programmable interconnect layers, embedding intellectual property (such as RAM and timing generators) and adding pre-designed features to reduce cycle-time (such as embedded clocks and test structures).
Yet structured ASICs are different from gate arrays in several ways. Instead of using interconnect metal to wire together a sea-of-transistors into the desired circuit as a gate array would, a structured ASIC wires together the array cells to create the desired circuit. Most structured ASIC architectures make use of an array cell structure that is repeated on the die multiple times to form the structured fabric.
Broadly speaking, there are three different types of fabrics in use. The first type of fabric is a fine-grained architecture that incorporates basic array cells similar in structure to the classic four-transistor gate-array core cell as illustrated in Fig 2. Higher level functions, such as I/O cells and test structures, are fully formed and embedded within the fabric.
2. A four-transistor gate-array base cell in a fine-grain architecture.
