|
|
Featured Design Center |
|
|
|
|
|
|
|
TI's expanding CPU line may be a problem
With the purchase of Luminary Micro and its Stellaris family of Cortex-M3 MCUs, Texas Instruments now has four distinct CPU architectures and is the only company with a CPU/DSP continuum. However, while it's an increasingly formidable MCU player, the incompatibility of these four CPU lines may be a problem.
|
|
|
Algorithms & Algorithm Development
Chat session reveals some of the "real" issues surrounding multicore
This live chat session was held during the EE Times Multicore Virtual Conference.
Alias, damned alias and statistics
There have been some recent articles discussing aliasing. Does it need fixing, and does fixing it cause another problem elsewhere? ADLE's resident 'filter wizard' sheds light on the true impact of impostor frequencies.
Applying Chaos Theory to Embedded Applications
A unique chaotic-expansion formula that can be used to approximate chaotic sequences, and where the coefficients of the expansion formula are matched to the sequence through linear determination.
See all Algorithms & Algorithm Development »
System-Level Design
Tutorial: the new JEDEC interface standard for data converters, Part 1 of 3
Understand the design implications of JESD204A for high-speed analog/digital and digital/analog converters
Digital representations of analog systems for control system applications
This tutorial shows how digital controllers can be created from an analog (or continuous) model. Included is an examination of the "Tustin's method" and "hold equivalence" methods of converting from the analog to digital domain.
Altium Design Contest winner: yyCAN review
This article by James Brakefield, selected as the winner of the Altium Design Contest, describes his yyCAN controller (the name has multiple meanings) written in VHDL.
See all System-Level Design »
FPGAs & Processors
Rapid debug of serial buses in FPGAs
Low-speed serial buses remain prevalent in computer, semiconductor, aero/defense, communications, consumer automotive, medical, test and measurement industries. Serial buses such as I2C, SPI, CAN, LIN, and RS-232 are often key points for debugging designs with FPGAs which higher speed serial buses quickly pass data from chip to chip. Historically, capturing and decoding the information required significant manual effort if using an oscilloscope or the purchase of custom tools. Oscilloscope vendors now incorporate significant application technology that simplifies debug of low-speed serial buses.
The ConnX Baseband Engine and its application in LTE
The ConnX Baseband Engine from Tensilica addresses the baseband demands of 3G and 4G networks. This feature details the architecture and its capabilities and how to apply it for LTE with MIMO.
Bridging the voltage gap with FPGAs
FPGAs have become sensitive to power-design considerations in supporting multiple voltage options for I/O banks. This paper examines how some low-power FPGAs leverage the VCCI of each I/O bank to determine the voltage level of its I/Os, ranging from 1.2 V up to 3.3 V.
See all FPGAs & Processors »
Benchmarking & Product Selection
And Stellaris Makes Four: But TI's expanding CPU line may work against it
With the purchase of Luminary Micro and its Stellaris family of Cortex-M3 MCUs, Texas Instruments now has four distinct CPU architectures and is the only company with a CPU/DSP continuum. However, while it's an increasingly formidable MCU player, the incompatibility of these four CPU lines may be a problem.
Analysis: APTX intro's cognitive audio encoder, drops hardware division
APTX recently announced its new apt-X Scalable that can select an encoding scheme based on the signal's characteristics. Oddly, the company also sold its hardware division. BDTI's Jeff Bier takes a look at both the technology and business implications.
Analysis of Microchip's PIC32 library
With the 32-bit MIPS 4K core, Microchip is now competing with the ARM juggernaut so offering optimized DSP libraries for the PIC32 is a good strategy. BDTI examines the library, in particular it looks at how it stacks up against ST Micro's ARM Cortex-M3-based STM32 library offering.
See all Benchmarking & Product Selection »
Tools & IP
Prep patents with reverse engineering in mind
Any company that files patents as part of its intellectual property strategy should be actively thinking about the end use of those assets.
Secure by Design: Using a Microkernel RTOS to Build Secure, Fault-Tolerant Systems
When securing an embedded system, a protective barrier facing the external threats is a good start. But security within the system is still required to prevent the damage if an attack breaks through. This technical paper looks at how an RTOS can provide mechanisms to prevent software processes from damaging other processes within the system.
DSPs evolving, but coding/debug needs to catch up or we're in trouble
DSPs are great, but they will only sort themselves out when the language to program and then simulate and debug the code improves, else, we are going to have more glitches as code gets reused and more band aids put around it to do more things.
See all Tools & IP »
See all Design Center »
|
|
|
DSP DESIGN CENTER ARCHIVE
|
| |
About the DSP DesignLine How-To Section
DSP DesignLine's How-To section delivers engineering articles focused on the design and development of wireless handsets and base stations—including 3G, 4G, and WiMAX—portable media players and other consumer electronics, VoIP, IPTV, audio and video, and motor control.
|
|
|
