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Featured Design Center |
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Efficient UMTS Turbo MAP decoding on a DSP
ADI lays out an efficient implementation of a UMTS Turbo MAP decoder. Optimization techniques are presented which allow the implementation to compute one LLR output in 36 cycles.
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Algorithms & Algorithm Development
How to get ready for WiMAX
Are you looking for a comprehensive way to get up to speed on OFDM and MIMO? Here is some information on a new seminar, and some recent related articles that might help get you started.
Error-Resilient Coding for Audio Communication - Part 2: Lapped transform codecs
Part 2 of an excerpt from "Multimedia Over IP and Wireless Networks" examines loss concealment techniques for overlapped transform based codecs.
A six step process for migrating embedded C into a C++ object-oriented framework
Using a standard timer, Dirk Braun describes a six step process to migrate embedded C code into a C++ object-oriented framework and create classes that represent a type of on-chip hardware peripheral.
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System-Level Design
How Bluetooth and 802.11 will team up to deliver high speed wireless connections
The heart of Bluetooth high-speed technology is the concept of the Generic Alternate MAC/PHY (Generic AMP), an innovative solution for radio substitution that allows the Bluetooth stack to dynamically select the right radio for any application.
Power management in mobile devices--A view of energy conservation--Part V
The gaps grow larger between what mobile devices can do and the amount of energy engineers can deliver. Chapter 2 from Power Management in Mobile Devices: Hierarchical View of Energy Conservation is an in-depth look at the power consumption, energy types, process and transistor technology, and packaging issues inherent in mobile device design. Part V discusses low power packaging techniques
20th Anniversary article: Full simulations with partial hardware
What do you do when the hardware team needs working software to check out the system and the software team needs stable hardware to complete their design work? Adding partially operational simulator hardware can improve the effieciency and flexibility of your existing simulator or emulator.
See all System-Level Design »
FPGAs & Processors
Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 1)
An MPPA having hundreds of processors can simplify video and imaging software development for embedded applications. Each processor in an MPPA is strictly encapsulated, accessing only its own code and memory. This architecture provides a very different programming model, one where each processor devotes separate channels for each type of input and output data it needs to communicate with other processors, and there are no shared memory bottlenecks.
Efficient UMTS Turbo MAP decoding on a DSP
ADI lays out an efficient implementation of a UMTS Turbo MAP decoder. Optimization techniques are presented which allow the implementation to compute one LLR output in 36 cycles.
Making design choices between DSP and FPGA
System designers face a number of key questions during the architecture phase of their project. Increasingly, one of those questions is whether to use a field-programmable gate array or a digital signal processor.
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Benchmarking & Product Selection
Analysis: 3DLabs takes massive parallelism to portables
3DLabs' processor incorporates two ARM9 processors and a SIMD array of 24 32-bit floating-point processing elements. BDTI explains how it works.
Analysis: IBM's Cell for Embedded?
BDTI recently investigated the current state of Cell products, and whether the architecture is likely to get significant traction in embedded applications.
Embedded multicore reversing DSP-GPP convergence
As multicore chips make waves in the embedded software industry, the convergence of DSP and non-DSP processors has changed to a renewed divergence, with developers turning their eyes, respectively, toward massively parallel multicore and SMP chips.
See all Benchmarking & Product Selection »
Tools & IP
How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 2
Using advanced HDLs like SystemVerilog, current hardware modeling styles can be enhanced both in terms of abstraction levels and overall efficiency.
Tip: FFTs in LabVIEW FPGA
Here's how to use the Fast Fourier Transform (FFT) block for National Instruments' LabVIEW FPGA.
Insuring silicon Intellectual Property interoperability with OCP consensus profiles
The OCP-IP Consortiumhas defined Open Core Protocol (OCP) subsets or profiles which are designed to give engineers standardized configurations of OCP options for specific system use cases, ensuring interoperability without conversion.
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DSP DESIGN CENTER ARCHIVE
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About the DSP DesignLine How-To Section
DSP DesignLine's How-To section delivers engineering articles focused on the design and development of wireless handsets and base stations—including 3G, 4G, and WiMAX—portable media players and other consumer electronics, VoIP, IPTV, audio and video, and motor control.
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