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Featured Design Center |
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Video codecs, part 5: Scalable video codec (SVC)
Part 5 introduces scalable video coders (SVC) and explores motion compensated temporal filtering (MCTF), including a discussion of detecting covered pixels and bi-directional MCTF.
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Algorithms & Algorithm Development
Video codecs, part 5: Scalable video codec (SVC)
Part 5 introduces scalable video coders (SVC) and explores motion compensated temporal filtering (MCTF), including a discussion of detecting covered pixels and bi-directional MCTF.
Codecs: 24 design ideas for video and imaging
Codecs are essential to video and image processing. Here's a roundup of codec-related design articles.
DSP Tricks: Efficient Polynomial Evaluation
Richard G. Lyons, author of "Understanding Digital Signal Processing," provides some tips on efficient polynomial evaluation.
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System-Level Design
Fingerprint identification with Blackfin
This article explains the basics of biometrics, and shows how to create an fingerprint identification system with the Blackfin processor and Atmel's FingerChip sensor.
What you need to know about imaging solutions for camera phones
Today's camera phones will give way to 'intelligent' phones that use their image camera subsystems in ways beyond simple still image or video capture. Here is a look at how to select the right image sensor and other components in the camera systems--things you 'must know' for your designs--in order to stay ahead of the pack.
Judging video quality and artifacts with human subjects and objective metrics
How video artifacts originate, and how to measure their severity using human test subjects and automated algorithm-based systems.
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FPGAs & Processors
Virtualization for embedded X86 multiprocessor applications
The addition of Intel's VT hardware technology to its x86 CPUs makes possible the creation of a software-based embedded virtual machine manager.
How to interface FPGAs to microcontrollers
Neither standard product microcontrollers nor FPGAs were developed to communicate with each other efficiently, so interfacing the two can be a challenge.
Code techniques for processor pipeline optimization: Part 3
In the final in a three part series, the authors of "Programming with Wireless MMX Technology," explain the performance implications of a processor's pipeline structure. Part 3: control-oriented optimizations.
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Benchmarking & Product Selection
Analysis: TI focuses on low power with new chips
BDTI analyzes TI's low-power variants of its four key processor product lines: C55x, C64x+, C67x, and OMAP.
Comment: Application processor--say what?
The term "application processor" really annoys me. What kind of processor doesn't run applications?
Comment: Risky business
If you were getting ready to buy a new car, you wouldn't make your choice based solely on the vendor's marketing claims. Yet that's exactly what some design engineers do when they choose a processing engine.
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Tools & IP
Data compression for high-speed DSP, part 2
Samplify benchmarks its compression algorithm against LZ-based lossless compression algorithms and consumer compression algorithms such as MP3, JPEG, and H.264.
Data compression for high-speed DSP, part 1
New data compression technologies can save power and cost in applications with sampling rates above 10 Msamples/sec. Here's how it works.
ESL handoff: closer than you think
Any viable design methodology requires tight links to implementation, and to meet this need a new generation of High-Level Synthesis tools is emerging, based on SystemC.
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DSP DESIGN CENTER ARCHIVE
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About the DSP DesignLine How-To Section
DSP DesignLine's How-To section delivers engineering articles focused on the design and development of wireless handsets and base stations—including 3G, 4G, and WiMAX—portable media players and other consumer electronics, VoIP, IPTV, audio and video, and motor control.
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