By Bill Witowsky

As Moore's Law shows no sign of slowing by 2020 with respect to transistor density, chip designers can be expected to create even more complex systems on chip (SoCs) compared to today's already complicated SoCs. Given that frequency and voltage scaling do not continue to scale due to power/heat dissipation, it is clear that higher performance must be achieved through a heterogeneous mix of highly parallel processing elements.

The cost to develop these SoCs will require that they can be easily repurposed across multiple applications. To achieve this, the inherent functionality of a SoC will be defined primarily by the software. We've already seen this happen with DSPs where signal-processing functions are implemented in software instead of fixed hardware blocks. With SoCs, the external interfaces, including radio technology and communications protocols, will be defined in software as well.

This approach places a huge emphasis on software, not only in terms of the sheer quantity of embedded software that will run on a year-2020 SoC, but also in what advanced tools will be required for complex system modeling, design, implementation, tuning and debugging. New programming languages, development methodologies and OS extensions/constructs will also be required to better enable parallel processing, as well as a stable ecosystem where software from different vendors can readily coexist and cooperate.

While power, performance and area will continue to be important, customers will place increased emphasis on protecting their software investment, demanding SoC platforms that abstract and virtualize design with tools that manage and hide complexity. Those vendors that can provide the most compelling software platforms will be the most successful.

So what will we do with all of this processing capacity? By scaling up performance we'll be able to solve problems that were previously not practical from a cost, power and/or area perspective. Alternatively, devices can scale down for ultra-low power and miniaturization.

It's hard to predict the future, but the underlying technological advances we'll see by 2020 will definitely change the way we live. The ubiquitous communications enabled by software-defined radio will extend to automatically take into account our current locale through highly adaptive and context-sensitive algorithms, tearing down the final distance barriers to give people access to their world anytime and anywhere. This automation will be partially enabled through sensor networks. For example, carpet sensors detecting dirt will invoke the vacuum cleaner. In hospitals, patients will be monitored from check-in to check-out with the information being intelligently processed and correlated automatically.

Next-generation speech recognition and natural language understanding will redefine how we interact with all machines, not just our PCs and mobile devices but our cars, our home entertainments systems and the ATM. Nor will we have to speak into a special device; just saying out loud, "It's too hot," will trigger the air conditioning. We'll also see extended information mining including not only searches for text but also for video and audio based on context and natural language understanding.

For medical applications, advances in imaging and processing will save lives as well as improve overall quality of life. Robotics and virtual reality technology will provide more lifelike experiences " from learning to fly a plane or performing a surgical procedure to interactive gaming and movies.

About the author

By Reid Tatge

Customers need chips, tools and software that match the specific needs of their application. In addition, they need everything to be simple to design into a product, easy to program efficiently, ultra-low power and ultra-low cost, available early in the end-product's preferred life-cycle and broadly supported by third parties. In 2020, I expect customer requirements to stay pretty much the same, but the underlying technology and how we develop it will be vastly different and far more complex than what we provide now.

From a hardware perspective, these future systems on chip (SoCs) will bring multiple digital signal processor (DSP) and general-purpose processor (GPP) cores together with custom hardware accelerators into a heterogeneous architecture loosely coupled with an asynchronous interconnect. In addition, these devices will have a non-uniform memory architecture and be designed for ultra-low power consumption.

Designing such complex architectures from scratch will no longer be feasible, both from a cost and time-to-market standpoint. Instead, devices will be designed using an iterative approach that relies on reconfigurable system modeling tools, such as G3-type compilation tools that support a rapid design methodology. Specifically, the topology of the SoC will be tunable according to the particular application domain at the individual processor node and memory subsystem level. The chief advantage of this approach is that it leads to completed SoC designs in months, not years.

The next challenge for SoC designers will be making them easy to program so developers can view the system as a loosely-coupled network of processors and be able to access the variety of available processing capabilities without having to involve themselves in all the low-level details that arise in multiprocessor architectures. Additionally, developers will need to be able to program in a HLL (high-level language) while achieving high-performance efficiency. Development tools for these SoCs will support program partitioning, system visualization, multi-core compilation and pre-hardware simulation as well as provide a reliable OS designed to manage the unique characteristics of multi-core architectures.

While it is difficult to anticipate exactly how these SoC devices and development tools will manifest, I can eliminate a number of "promising" possibilities:

• Large, monolithic, mega-CPUs: These fantastically complex architectures take years to define and tune, and then, at least another year to design. Their development environments are closed not for any proprietary reasons but because only the architects can program them.
• Symmetric networks of commodity GPPs: While an outside contender, these architectures solve difficult problems with more of the same. Eventually they collapse under the weight of messaging, data stitching and other forms of overhead.
• Any architecture dependent upon "Magic" tools: It would certainly solve many problems if development tools could generate great code for any arbitrary CPU as well as automatically partition inherently serial programs onto a network of processors. Such a panacea will not be available by 2020.

By Gene Frantz

I have come to the conclusion that too many of us have no clue where we are going with technology. Rather, we are just busily moving forward and don't know if we are even moving in the right direction. It would seem that with our extensive experience in traveling we would understand a basic concept " to travel to a distant place requires two points:

1. Where I am
2. Where I want to end up at

The same goes for technology " we need to know where we are going to move in the right direction. So, I have challenged several of our senior technologists to think about what the state of the art will be in the year 2020. You might say that we need to have 20/20 vision for the year 2020. I have invited a number of technologists to provide their point of view (POV) of what the state of the art in IC technology will be in the year 2020, and I'm interested to hear what you have to say on the topic. But, since this is my blog, I will have the first and last word on what the year 2020 will hold for us.

So, here are my first thoughts on the topic.

• Processing elements will be single clock domains. After many years of assuming that Moore's law would give us faster and faster clock speeds, we have finally concluded that clock speed is no longer our friend. In fact, we should have noted that 15 years ago, but as we move forward, processing elements will be of the size that the CPU can communicate with all of its resources in one clock cycle.
• Systems will be made up of multiple processing elements. Integrated systems will be made up of many heterogeneous processing elements, each being a "single clock domain" processor.
• The processing elements will be arranged in a similar style as FPGAs today.
• We will take advantage of the third dimension. Integration using stacked die techniques (SIP) will be just as common as fully integrated SoC.
• All will be programmed with a high-level language. The development environment will have the ability to take into account all of the resources in the system. That is the microprocessors, DSPs, accelerators, peripherals, analog signal processors, analog peripherals, RF and other things I have forgotten about.
• IC designs will consist of smaller teams (5 to 10 designers) taking a shorter amount of time (6 to 12 months) to do the hardware design. Reuse will be the norm. While I am at it, let me explain that there are two definitions of "Reuse":
  
  

  1. I'll do such a good job on my design that everyone after me will use it.
  2. I don't have time to reinvent the wheel, so I need to find something that is close enough to what I need to meet the schedule.
  
  

  Unfortunately we use the first definition more than the second. Small design teams with short schedules will require us to use the latter definition. And, yes, there are companies already adopting this concept of reuse.

• The bulk of the innovation will be in the software on top of the hardware.
• Hardware will become part of the platform on which innovative designers will develop their ideas.

So, this is a sketch of how I see 2020. After a couple of POV papers from others at TI, I will come back with a conclusion. My colleagues will dive into topics such as programmability, tools and SoCs in the next few blogs. If you would like to share your view of 2020 with me, please comment or send me a private note.