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Today eASIC announced its Nextreme2 line of 45 nm structured ASICs* that promises to breathe new life into ASICs. Nextreme2 has many impressive features, but its main selling point is that it burns up to 5X less power than comparable FPGAs. That's a lot less power!
FPGAs have a reputation for being power hogs. Some of this reputation is undeserved. In some applications, FPGAs are actually burn less power than the alternatives. For example, FPGAs can burn less power than DSPs in high-performance signal-processing apps. However, FPGAs burn much more power than ASICs. That's where eASIC comes in.
FPGAs have several inherent features that increase power consumption. For example, FPGA contain SRAM that controls interconnects and look-up tables (LUTs). Because ASICs are hard-wired, they don't have this SRAM. Thus, FPGAs burn more power than equivalent ASICs.
eASIC says it achieves ASIC-like power by eliminating these power-hungry features. The 90 nm Nextreme product eliminated the SRAM for interconnects. Nextreme2 takes things further by eliminating the SRAM for LUTs as well. Nextreme also saves power by:
- Moving to a low-power 45 nm process
- Offering a three voltage options, include a low-voltage 1.0 V product
- Adding via power gating, which permanently removes power from unused logic
- Providing clock gating, which temporarily remove the clock from idle logic
Like all structured ASICs, Nextreme2 has its disadvantages, such as a 6-week turn-around for hardware spins. (This is only a disadvantage in comparison to FPGAs. Compared to traditional ASICs, this turn-around is very short.) However, Nextreme2's low power consumption makes it worth a close look.
*eASIC likes to call its offering a "zero mask-charge ASIC," presumably because the term structured ASIC has been associated with business failure in recent years. (See LSI, Fujitsu, NEC, Oki and Toshiba, for example.) Nonetheless, the products are clearly structured ASICs (which are also sometimes called platform ASICs).
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