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To make FPGAs accessible to DSP engineers without hardware design expertise, FPGA and tool vendors have developed tools that allow FPGAs to be programmed in high-level behavioral languages such as MATLAB and C, or graphical languages like Simulink.
In this article we explore Agility's PixelStreams, a graphical programming tool designed specifically for image and video algorithms. First, we examine the basic PixelStreams design flow and how it works with Agility's C-based design environment, DK Design Suite. Then, to illustrate the flow we implement the Sobel edge detection algorithm, taking NTSC TV as an input and outputting edge-detected VGA. To aid in our review, Agility provided a single-seat license to its tools free of charge.
What exactly is PixelStreams?
PixelStreams is a graphical programming environment coupled with a library of highly parameterizable image and video processing IP cores. Using the PixelStreams graphical user interface (GUI), shown in Figure 1, users implement their algorithm by configuring IP blocks, or "filters" in Agility's nomenclature, and connecting them via configurable "streams".
(Click to enlarge)
Figure 1. PixelStreams GUI with sample application.
The Basic Design Flow
Once a design has been created in the GUI, it is compiled to Agility's C language variant, Handel-C. Handel-C is a superset of ANSI-C with special constructs that enable more efficient hardware utilization. For instance, Handel-C can specify whether statements should be executed in parallel and which should be executed sequentially. (To learn more about Handel-C, see the Agility home page.)
The Handel-C code generated by PixelStreams is then sent to Agility's C-based development environment, DK Design Suite (Figure 2.). In DK Design Suite, designers can modify the generated Handel-C or add new code. In addition to providing an IDE for modifying and debugging Handel-C, DK Design Suite is also a full featured Electronic System Level (ESL) deign environment. It features:
- Cycle accurate hardware simulation
- Simulink/MATLAB and RTL co-simulation
- The ability to integrate C/C++ code for testbench creation
- Optimized synthesis for Handel-C and SystemC
- Extensive IP libraries
DK Design Suite then synthesizes the Handel-C into an EDIF netlist optimized for the target FPGA. Optimization is done using advanced synthesis techniques that exploit architectural features specific to the targeted FPGA. For instance, DK Design Suite utilizes hard-wired DSP blocks and memories where advantageous. Supported FPGAs include a wide range of high-density devices from Altera and Xilinx.
In the final step, DK Design Suite launches the user's 3rd party synthesis tools, which perform place and route and generate the final FPGA bitfile.
Figure 2. DK Design Suite tool flow.
Next Step: Hardware
To ease development and provide a complete "out of the box" solution, Agility offers its RC Series of FPGA development boards. The boards feature Xilinx FPGAs coupled with video-oriented I/O and peripherals. For example, the RC340 shown in Figure 3 is based on a Xilinx Virtex-4. The RC340 with the Virtex-4 offers 4 banks of on-board memory totaling 32 Mbytes and dual video support including composite, s-video, DVI and VGA.
(Click to enlarge)
Figure 3. RC340 FPGA development platform.
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